When designing an integrated circuit, a designer will use various electronic design automation (EDA) tools to describe the elements and functions that will be incorporated into the integrated circuit. For example, the designer may use a hardware description language, such as VHDL. A hardware description language allows the designer to describe the functions that are to be performed by the integrated circuit, without specifying the elements used to perform the functions. Software tools are available to translate the hardware description language into a gate level design that implements the specified functions. Alternatively, the designer may enter the gate level design directly. For example, drawing tools are available for entering gate level designs. Such designs may be represented by a schematic that has symbols to identify each element in a design. In the schematic, every element is represented by a symbol. Generation of the schematic may be accomplished manually or automatically.
In order to fabricate the integrated circuit, the schematic is translated into a physical layout. The physical layout is a description of how the design will be fabricated in the actual device. In other words, it is a physical representation of the elements in the schematic. Generating a physical layout is a time consuming process. Electronic design automation tools exist to generate a physical transistor layout with uniform gates. These types of gates are known as standard cells. However, in the case of non-standard cells, or custom cells, the layout engineer generates the physical transistor layout manually, for instance, by drawing it with a computer. For a typical integrated circuit, it may take months to generate a custom layout.
Thus, it would be highly desirable to improve the integrated circuit design process by providing a tool that can be used to automatically generate physical layouts for custom cells from a circuit schematic.